1. Field of the Invention
This invention relates to reshaping periodic waveforms to a selected duty cycle.
2. Description of Related Art
Clock signals are regularly timed periodic signals which are used to trigger elements in virtually all digital circuits. A typical clock signal is a square wave, i.e., a signal which is virtually always at either a logic "0" value or a logic "1" value, with sharply defined edges at transition times. For example, storing data into a register might be triggered by the rising edge of the clock signal, i.e., the transition from logic "0" to logic "1". A clock signal is often described in terms of its frequency, which is the number of full periods of the clock signal in a second, and its duty cycle, which is the fraction of each full period the clock signal spends at logic "1". The clock signal may also be described by the duty cycle skew, which is the difference between the fraction of each full period the clock signal spends at logic "1" and the fraction it spends at logic "0". An equivalent to frequency is the clock signals period or width, which is the duration in seconds of one full period.
Many digital circuits are "edge-triggered", i.e., triggered by an edge of the clock signal, and of those, many digital circuits have both elements which are triggered by the rising edge of the clock signal and elements which are triggered by the falling edge of the clock signal. Moreover, many digital circuits have signal paths which are time-critical; they depend on the clock signal's width being longer than some preselected time value. In such digital circuits, it can be critical that the duty cycle of the clock signal is exactly 50%. For example, if the clock signal has a frequency of 100 megahertz and therefore a period of 10 nanoseconds, circuits which require a time period of at least 4.9 nanoseconds will fail if the duty cycle varies outside the range 49% to 51%. Many digital circuits have even more stringent tolerances.
One known method is to start with a clock signal which is twice as fast, to couple the "doubled" clock signal to a divide-by-two counter, or to use a phase-locked loop (PLL) to generate a new clock signal which has about a 50% duty cycle. While this method is capable of achieving an approximately 50% duty cycle, it is not suitable when digital circuit tolerances are very stringent. Moreover, it often requires generating a clock signal which is at a higher frequency than can be stably achieved.
Accordingly, it would be advantageous to provide a superior technique for reshaping periodic waveforms to a selected duty cycle. The preferred selected duty cycle is 50%, but the same technique is capable of reshaping periodic waveforms to any selected duty cycle, such as 1%, 10%, 331/3%, or some other selected duty cycle.